HLayout
HLayout logoThick-film hybrid circuit layout CAD

Lay out hybrids, not PCBs.

HLayout designs the printed conductors, dielectric, resistor inks and glaze of a thick-film hybrid on its ceramic substrate, with packaged parts or wire-bonded bare dies. It takes a KiCad netlist in and sends Gerbers, bond diagrams, assembly drawings and 3D models out.

Download HLayout View on GitHub
Free and open source · GPL-3.0 · Windows, Linux and macOS
HLayout main window showing the ALU16 module: ten LCC packages on a two-conductor thick-film substrate with the layer list on the right
0.000 mmALU16 module · example 21 DBU = 1 µm
Built around the film stack

Every layer knows what it is

Print order, not layer numbers

Up to 64 GDSII layers, each given a role: conductor, dielectric, resistor ink, glaze, epoxy, die pads, wire bonds. Top views, 3D models and thermal analysis all stack them as they are fired.

Printed resistors from value and power

The Resistor Designer sizes each resistor from value, tolerance, power and ink, and the trim simulator models plunge and L-cut laser trimming.

Dielectric generated, not drawn

After routing, the dielectric sheet is rebuilt inside the I/O ring with a window at every via.

Schematic to manufacturing

One open-source workflow

Seven stages from circuit diagram to the files a print line, die bonder and test station need. The open-source tools are called from inside HLayout and their results come straight back into the design.

1

Schematic

Ref-des, pin and die-pad numbers, power nets.

KiCad
2

Technology & parts

Layers, libraries, bare dies, printed resistors.

HLayout
3

Placement

Auto Place from the netlist on a 50 µm grid.

HLayout
4

Nets & bonds

Net names and a wire bond from every die pad.

HLayout
5

Routing

Two conductors with vias, or one with jumpers.

Freerouting
6

Verify

DRC, netlist extraction, thermal, trim.

HLayout
7

Outputs

Gerber, DXF, pick and place, drawings, 3D.

FreeCAD
Open-source tool in the loopDone inside HLayout

KiCad .net · GDSII · Specctra DSN/SES · Gerber RS-274X · DXF · STEP · CSV · KiCad .pos

Key features

The tools a hybrid needs, in one editor

ROUTE

Autorouting with Freerouting

Your DRC rules set the widths and clearance. Wire-bond landings become bond fingers. The ALU16 chip-and-wire build routes 85 of 85 nets.

BOND

Chip-and-wire router

Single-conductor hybrids routed with wire-bond jumpers, plus a bond diagram CSV in bonding order for the wire bonder.

PLACE

Auto Place

Shortest weighted net length with power and ground counted, hot parts kept apart, and straight-line interconnects that follow every drag.

CHECK

DRC and netlist extraction

Widths, spacings, substrate-edge clearance and wire-bond length and angle, then copper connectivity compared against your nets.

HEAT

Thermal analysis and laser trim

Steady-state conduction through substrate and films gives each resistor, die and part a temperature against its limit, and a trim simulator shows plunge and L-cut trims step by step. See both tools

CAM

Manufacturing outputs

Gerber per print layer, DXF, pick-and-place centroids, test netlists and a one-step assembly drawing with pin, resistor and bond tables.

Example 5 · ALU8 chip and wire

One design, from layout to 3D

An 8-bit ALU built from six bare dies (two 54AS181 ALU slices and four 54LS gates) wire-bonded onto a two-conductor thick-film substrate, sealed in a 40-pin Kovar DIP package. 46 nets, placed by Auto Place from the netlist and routed with Freerouting.

ALU8 layout in HLayout: six dies with wire bonds, the 1st conductor in orange and 2nd conductor in purple over the dielectric, inside the 40-pin Kovar package
Layout. 1st conductor (orange) and 2nd conductor (purple) over the dielectric, dies wire-bonded to their fingers, 40 package pins round the edge.
The same ALU8 design in 3D: green dielectric with gold conductors and dark dies on a white alumina substrate, seated in a grey Kovar package with gold pins in green glass seals
The corresponding 3D view. The FreeCAD export of the same design: fired films at their real thickness, dies on their attach pads, and the substrate seated in the Kovar DIP40 with its glass-sealed pins.
Close-up of a 54AS181 die in 3D with gold wire bonds looping out to bond fingers on the conductor
Close-up. A 54AS181 die with its gold wire bonds looping out to the bond fingers.
The ALU8 assembly drawing on an A3 sheet: scaled top view, pin function table and title block
Assembly drawing. Built in one step: scaled top view, 40-pin function table and title block.
3D and documentation

See it fired before it is printed

Export the design to FreeCAD as one solid per film at its fired thickness, with real STEP bodies for chip capacitors, SOT and LCC packages, Kovar headers and bare dies. The SolidCraft view writes STEP, 3MF, STL or OBJ.

The ALU16 module rebuilt in 3D in FreeCAD, showing the substrate, conductor and dielectric films and the LCC packages
ALU16 rebuilt in FreeCAD from the exported macro.
Chip-and-wire ALU16: the whole substrate on the left and a die with wire bonds fanning out to bond fingers on the right
Chip-and-wire ALU16: bare dies wire-bonded to fingers on the 2nd conductor.
Consultancy and customisation

Need HLayout to fit your process?

HLayout is free to use. When you need it adapted to your line, extended with your own tools, or a design laid out for you, the author offers paid help built on the same open-source code.

Email support@h-layout.co.uk Write an email

Tell us about your process, the parts you use and what you want HLayout to do.

PROCESS

Process setup

Your layer stack in print order, film thicknesses, design rules, resistor inks and DRC rule sets, saved as a technology file your team reuses on every job.

LIBRARY

Part libraries and 3D models

Footprints, bare-die cells with numbered pads, headers and packages, each with a matching STEP model for the 3D view.

BUILD

Custom features

New tools, import and export formats, router rules or scripts for your workflow. Work built into HLayout stays open source under GPL-3.0.

LAYOUT

Hybrid layout design

From your KiCad schematic to placement, routing, DRC, thermal check, Gerbers, bond diagram and assembly drawing.

TEAM

Training and support

Hands-on sessions for your designers using your own parts and rules, and priority help when something stops your line.

Questions

Thick-film hybrid layout, answered

What is HLayout?

HLayout is free, open-source layout CAD for thick-film hybrid circuits and chip-and-wire microelectronic modules. It draws the printed conductors, dielectric, resistor inks and glaze on a ceramic substrate, places packaged parts and bare dies, routes them, checks the design and writes the manufacturing files.

What is a thick-film hybrid circuit?

A thick-film hybrid is a circuit whose conductors, insulating dielectric and resistors are screen-printed as pastes on a ceramic substrate, usually alumina, and fired. Chip components, packaged parts and bare semiconductor dies are then attached; bare dies are connected with wire bonds, which is called chip-and-wire assembly.

Does HLayout work with KiCad?

Yes. Draw the schematic in KiCad and export the netlist; HLayout reads it, places the parts with Auto Place and routes with Freerouting through a Specctra DSN/SES round trip. Die pads and pins can be numbered or named, such as E, B and C for a transistor die.

Can HLayout design thick-film printed resistors?

Yes. The Resistor Designer sizes each resistor from its value, tolerance and power: it picks the body width for the power, an aim value below target for laser trimming, the ink and the number of squares, then places the ink, terminations, glaze and dielectric keep-out. A trim simulator shows plunge and L-cut trims.

Which manufacturing outputs does it produce?

Gerber RS-274X for every print layer, DXF, pick-and-place files, bond lists for the wire bonder, test netlists, an assembly drawing with title block and pin table, and a 3D model of the fired substrate and parts for FreeCAD with STEP models.

Does it check wire bonds and design rules?

Yes. Design rule checks cover track widths, spacing, substrate-edge clearance and wire-bond length and departure angle. Netlist extraction compares the drawn copper and bonds with the schematic, and a thermal analysis estimates die and resistor temperatures.

Is HLayout really free, and which systems does it run on?

HLayout is free software under the GNU GPL v3.0 or later, with the full source on GitHub. Installers are available for Windows, Linux (Debian/Ubuntu) and macOS, and it can also run from source with Python.

Is training or help available?

Yes. A three-day hands-on training course takes an 8-bit ALU chip-and-wire design from netlist to Gerbers and 3D, and process setup, part libraries, custom features, layout design and support are available from support@h-layout.co.uk.

Ready to lay out your first hybrid?

Free and open source under GPL-3.0. Installers for Windows, Linux and macOS, built from the public source by the project's CI.

Download HLayout